Field of the Invention
The subject matter of this application relates to microelectronic packages which comprise both logic and memory die and more particularly to packages in which enhanced heat transfer is provided.
Description of the Related Art
Semiconductor die or chips are flat bodies with contacts disposed on the front surface that are connected to the internal electrical circuitry of the chip itself. Semiconductor chips are typically packaged with substrates to form microelectronic packages having terminals that are electrically connected to the chip contacts. The package may then be connected to test equipment to determine whether the packaged device conforms to a desired performance standard. Once tested, the package may be connected to a larger circuit, e.g., a circuit in an electronic product such as a computer or a cell phone.
In order to save space certain conventional designs have stacked multiple microelectronic elements or semiconductor chips within a package. This allows the package to occupy a surface area on a substrate that is less than the total surface area of the chips in the stack. However, conventional stacked packages have disadvantages of complexity, cost, thickness and testability.
Microelectronic elements of different types can be combined within the same package to provide faster and higher bandwidth connections between them. Combining semiconductor chips which have logic circuitry thereon with other types of chips can pose particular challenges. High bandwidth logic circuitry may require that connections between the logic chip and the substrate be in large numbers and as short as possible, favoring a flip-chip connection between the logic chip and the substrate. Chips within the package which implement other functions can be placed at other positions in the package so as not to interfere with the high bandwidth requirements of the logic chip. However, logic chips can generate much heat which needs to be shed to permit proper operation. Heat transfer from the logic chip to the outside can be impeded when another chip in the assembly substantially or completely covers an area of the logic chip, and can be further impeded when the another chip in the package is also operating, such that that heat is an even greater challenge to address.
For example, as seen in FIG. 1, in a prior art assembly including a microelectronic package 10, a logic chip 12 is flip-chip mounted to a substrate 14 in the microelectronic package, and the package 10 in turn is surface mounted to a circuit panel 20, such as through a ball grid array 22. As further seen in FIG. 1, another component 30 such as a chip or packaged chip of a different type than the logic chip 12 can be positioned above the logic chip 12 and electrically interconnected with the package 10, either through circuitry internal to or external to the package 10. Component 30 is provided within the same or a different microelectronic package as the logic chip. Lower bandwidth connections may be provided between the other component 30 and the substrate 14 than as provided between the logic chip 12 and the substrate 14. The assembly may be additionally coupled with a heat spreader 32 as seen in FIG. 1 or other component disposed above the component 30.
The assembly shown in FIG. 1 faces a particular challenge in shedding heat from the logic chip 12. The presence of the other component 30 can impede the transfer of heat to the heat spreader 32 as it may not be a very good thermal conductor, and the heat generated within the other component 30 may decrease the heat gradient between the logic chip 14 and the heat spreader 32, causing the rate of heat transfer between them to decrease. Excessive heat can decrease the performance of chips in a microelectronic package and can impact short term operation and long-term reliability.
In light of the foregoing, it would be desirable to provide a multi-chip microelectronic package which has features which facilitate high bandwidth connections between a logic chip and a substrate, and permit another type of chip to be positioned within the package and interconnected with the logic chip without sacrificing the thermal performance of the package.
Size is a significant consideration in any physical arrangement of chips. The demand for more compact physical arrangements of chips has become even more intense with the rapid progress of portable electronic devices. Merely by way of example, devices commonly referred to as “smart phones” integrate the functions of a cellular telephone with powerful data processors, memory and ancillary devices such as global positioning system receivers, electronic cameras, and local area network connections along with high-resolution displays and associated image processing chips. Such devices can provide capabilities such as full internet connectivity, entertainment including full-resolution video, navigation, electronic banking and more, all in a pocket-size device. Complex portable devices require packing numerous chips into a small space. Moreover, some of the chips have many input and output connections, commonly referred to as “I/Os.” These I/Os must be interconnected with the I/Os of other chips. The components which form the interconnections should not greatly increase the size of the assembly. Similar needs arise in other applications as, for example, in data servers such as those used in internet search engines where increased performance and size reduction are needed.
Semiconductor chips are commonly packaged in single- or multiple-chip packages and assemblies. Each package has many electrical connections for carrying signals, power and ground between terminals and the chips therein. The electrical connections can include different kinds of conductors such as horizontal conductors, e.g., traces, beam leads, etc., which extend in a horizontal direction relative to a contact-bearing surface of a chip, vertical conductors such as vias, which extend in a vertical direction relative to the surface of the chip, and wire bonds which extend in both horizontal and vertical directions relative to the surface of the chip.
As manufacturers of smartphones, tablets and other devices constantly seek increased performance and greater circuit density the trend for these devices is to provide ever greater functional capabilities in an amount of space on a circuit panel that may stay the same or decrease over time. In light of the foregoing, certain improvements can be made in the structure of microelectronic packages and assemblies which comprise a microelectronic package.
In spite of the above advances, there remains a need for improved multi-chip packages and especially multi-chip packages which incorporate a logic chip and another type of chip such as dynamic random access memory (“DRAM”) chip which provide high logic bandwidth and improved thermal characteristics.